1. Field of the Invention
Example embodiments relate to a storage device to selectively activate memory chips. More particularly, example embodiments relate to a solid state disk/device (SSD) storage device including a circuit capable of generating a plurality of memory chip activation signals to selectively activate memory chips by combining existing chip enable (CE) signals to increase memory capacity without additional chip enable signals.
2. Description of the Related Art
Recently, solid state disks/devices (SSDs) have been used as data storage devices instead of hard disks, because SSDs have lower power consumption, noise, and weight, due to the absence of a mechanical driving device, compared to a hard disk.
SSDs employ flash memories or flash memory chips as storage media and the data storage capability of an SSD mainly depends on a controller to control the SSD. The controller generates signals to control the flash memories of the SSD, including chip enable control signals corresponding in number to the flash memories. Thus, increasing SSD memories (i.e., storage capacity of the SSD) requires chip enable control signals corresponding in number to the SSD memories.
Present technology makes it possible to connect memory chips only by the number of chip enable (CE) signals supported by a controller. In other words, a total number of memory chips that can be mounted on an SSD is limited by a total number of CE signals. A double stack package (DSP) includes two memory chips, such that a total number of memory chips that can be mounted on an SSD is 2*(total number of CEs).
That is, it is necessary to increase chip enable control signals in order to increase memories for a high capacity SSD. This, in turn, requires modification of hardware and a production process.